1. Field of the Invention
The invention disclosed herein relates generally to testing processes and measurements of device parameters of power semiconductor device. More particularly, this invention relates to a new and more accurate measurement configuration and process to more conveniently obtain accurate device parameters on the wafer level of a semiconductor device.
2. Description of the Relevant Art
The technologies of applying power MOSFET transistors to switch the inductive load are still confronted with technical difficulties and limitations. Specifically, conventional test configurations and processes of measurement are still limited by the difficulties that an unclamped inductive switching (UIS) current cannot be conveniently and accurately set during the UIS test processes of a MOSFET power transistor. The difficulties are especially pronounced when an UIS test is carried out in the wafer level where probe card and cables introduce parasitic inductance thus causes measurement deviations to the UIS current.
During an unclamped inductive switching (UIS) operation, the drain to source junction of the power MOSFET transistor is forced into an avalanche breakdown during the off period of the switching cycles. If the MOSFET device is not properly designed, the power MOSFET may be destroyed by a voltage snap back during the avalanche breakdown. Due to this concern, the capability of a MOSFET to carry out repetitive unclamped inductive switching (UIS) becomes an important performance parameter of the MOSFET power transistors when these transistors are designed for switch applications. In order to assure the quality and reliability of the power MOSFET, it is necessary to carry out repetitive tests of a power MOSFET transistor.
Referring to FIG. 1 for a typical operation for carrying out an UIS testing of a power MOSFET. The test begins with a step of first turning on the MOSFET transistor 10 until the current, as that represented by the symbol I, in the inductor 20 reaches a predetermined value. Then the MOSFET transistor 10 is turned off and forced into an avalanche breakdown. Using a power supply 15 connected to the gate of the power MOSFET 10, such cycles are repeated again until the MOSFET transistor 10 is destroyed and the number of cycles is recorded.
When a MOSFET power transistor fails under the unclamped inductive switching test, all the terminals of the MOSFET transistor 10 are short circuited together. The failure of the MOSFET transistor is detected by detecting a short circuit condition. However, as will be further discussed below, in the wafer level UIS testing processes, the detection of MOSFET failure requires an accurate measurement of the UIS current. The UIS current, i.e., I, is set by turning on the MOSFET 10 for a specific period of time depending on the inductor value as defined by I=(V/L)* Δt, where V is the power supply voltage 30, L is the inductance of the inductor 20 and Δt is the pulse-width of the gate drive to the MOSFET 10. As shown in the equation, any uncertainty the inductance (L) or power supply voltage will cause uncertainty in the current (I).
Typical processes of conducting an UIS testing of a package power MOSFET transistor is usually performed by inserting the transistor in a socket connected to a circuit similar to FIG. 1. The socket is an integral part of the circuit, so the inductance of the circuit is well defined. The UIS current is typical set by adjusting the pulse width of the gate signal to the MOSFET using the equation:I=(V/L)*Δt  (1)
FIG. 2 illustrates the typical condition of a wafer-level UIS testing. The terminals of the power MOSFET 10 are connected using probes and cables. The probes and cables add parasitic inductance 40 to the circuit. This parasitic inductance 40 changes with probe configuration and cable length and position. Setting the UIS current by simply adjusting a fixed pulse width of the gate drive to the MOSFET transistor becomes inaccurate and unreliable. For these reasons, in order to carry out accurate UIS tests, there is a need to accurately set the UIS current in the wafer level UIS testing.
Therefore, a need still exists in the art to provide an improved device design and test configurations and methods to overcome the above discussed limitations and difficulties.